Stop me if you've heard this one: "A secretive, venture-backed startup company walks into a bar and announces that it plans to take on Intel by producing a low-power x86 processor aimed (initially?) at portables and laptops."
No, this isn't a joke about about Transmeta, though former Transmeta CEO Matt Perry is also CEO of the mysterious startup in question. Just about the only thing that's publicly known about this new x86 processor company is its name and its location: Montalvo Systems, based in—where else?—Santa Clara, California. All of the rest of the information to leak out about Montalvo comes courtesy of two recent stories by CNet's Michael Kanellos, who has a source that has been feeding him the goods on the startup. Kanellos has also dug up some patents filed at the WIPO, both of which provide additional insight into Montalvo Systems' plans.
From my reading of Kanellos' report and my admittedly hasty examination of the patents that Montalvo has filed in the US and internationally, it looks like the company will rely on at least two tricks to get x86 performance/watt ratios up enough to be able to make a go of dethroning Intel's Core 2 Duo.
The first trick that the company uses is an asymmetrical multicore approach, which Kanellos likens to IBM's Cell. Something tells me that whatever Montalvo has in mind, the only substantial thing that it could possibly have in common with Cell is that it can be generally described as an asymmetric multiprocessor on a chip. Anyway, Kanellos claims that Montalvo's chip mixes a more robust, larger-footprint core with multiple smaller, more lightweight, lower-power cores so that the processor can use the smaller cores for less intensive compute work and the larger cores when more muscle is needed.
The second trick, which I was able to sort out from looking through Montalvo's patents, is that the chip contains some sort of large pool of cache joined to a fairly robust control unit that can service DMA and DRAM requests by itself without waking the main processor. One suggestion from the patent is that you could put a highly compressed framebuffer in this cache and have an IGP read from it and decompress it without waking the CPU. Ultimately, the "buffer/mini-cache" (as the patent calls it) can be used for any type of non-cacheable traffic, with the control unit and cache servicing high-bandwidth DMA requests of any type without the processor's intervention.
There's no way for me to evaluate Montalvo's technology based on some reported rumors and an afternoon with a handful of patents, so I won't even bother to try to evaluate whether the company has a chance against even a small established player like VIA, much less Intel. But I will suggest a few general reasons why I'm skeptical.
No silver bullets
First, non-process-based power efficiency improvements from one processor to the next are like all other types of generational advances in processors—each generational jump in efficiency or raw performance is the cumulative result of many small tricks and tweaks, each of which contributes a few percentage points to the overall "20 percent performance improvement" claims that you typically see with a new processor.
My point is that there's never really a "silver bullet" for getting that magical double-digit improvement to whatever metric you're trying to improve, at least not at this mature stage in microprocessor evolution. You just make a whole bunch of refinements to an existing design (yours or someone else's) to get yourself over the hump. So if someone actually does come up with a way to remix processor microarchitecture and/or the cache hierarchy that gives them, say, a 15 percent or greater performance per watt boost over Intel on mainstream consumer workloads, I'll eat my hat. And if the company that buys that winning lottery ticket happens to be Montalvo, I'll eat your hat.
The second point that I want to make is that Intel has already announced (or rather, officially acknowledged the existence of) a forthcoming product family that consists of multiple small, low-power x86 cores on a single die. The company also has a large library of core designs of varying degrees of robustness. So if asymmetric multiprocessing turns out to be anything like a silver bullet for power efficiency, Intel could announce a competing product in short order.
No, this isn't a joke about about Transmeta, though former Transmeta CEO Matt Perry is also CEO of the mysterious startup in question. Just about the only thing that's publicly known about this new x86 processor company is its name and its location: Montalvo Systems, based in—where else?—Santa Clara, California. All of the rest of the information to leak out about Montalvo comes courtesy of two recent stories by CNet's Michael Kanellos, who has a source that has been feeding him the goods on the startup. Kanellos has also dug up some patents filed at the WIPO, both of which provide additional insight into Montalvo Systems' plans.
From my reading of Kanellos' report and my admittedly hasty examination of the patents that Montalvo has filed in the US and internationally, it looks like the company will rely on at least two tricks to get x86 performance/watt ratios up enough to be able to make a go of dethroning Intel's Core 2 Duo.
The first trick that the company uses is an asymmetrical multicore approach, which Kanellos likens to IBM's Cell. Something tells me that whatever Montalvo has in mind, the only substantial thing that it could possibly have in common with Cell is that it can be generally described as an asymmetric multiprocessor on a chip. Anyway, Kanellos claims that Montalvo's chip mixes a more robust, larger-footprint core with multiple smaller, more lightweight, lower-power cores so that the processor can use the smaller cores for less intensive compute work and the larger cores when more muscle is needed.
The second trick, which I was able to sort out from looking through Montalvo's patents, is that the chip contains some sort of large pool of cache joined to a fairly robust control unit that can service DMA and DRAM requests by itself without waking the main processor. One suggestion from the patent is that you could put a highly compressed framebuffer in this cache and have an IGP read from it and decompress it without waking the CPU. Ultimately, the "buffer/mini-cache" (as the patent calls it) can be used for any type of non-cacheable traffic, with the control unit and cache servicing high-bandwidth DMA requests of any type without the processor's intervention.
There's no way for me to evaluate Montalvo's technology based on some reported rumors and an afternoon with a handful of patents, so I won't even bother to try to evaluate whether the company has a chance against even a small established player like VIA, much less Intel. But I will suggest a few general reasons why I'm skeptical.
No silver bullets
First, non-process-based power efficiency improvements from one processor to the next are like all other types of generational advances in processors—each generational jump in efficiency or raw performance is the cumulative result of many small tricks and tweaks, each of which contributes a few percentage points to the overall "20 percent performance improvement" claims that you typically see with a new processor.
My point is that there's never really a "silver bullet" for getting that magical double-digit improvement to whatever metric you're trying to improve, at least not at this mature stage in microprocessor evolution. You just make a whole bunch of refinements to an existing design (yours or someone else's) to get yourself over the hump. So if someone actually does come up with a way to remix processor microarchitecture and/or the cache hierarchy that gives them, say, a 15 percent or greater performance per watt boost over Intel on mainstream consumer workloads, I'll eat my hat. And if the company that buys that winning lottery ticket happens to be Montalvo, I'll eat your hat.
The second point that I want to make is that Intel has already announced (or rather, officially acknowledged the existence of) a forthcoming product family that consists of multiple small, low-power x86 cores on a single die. The company also has a large library of core designs of varying degrees of robustness. So if asymmetric multiprocessing turns out to be anything like a silver bullet for power efficiency, Intel could announce a competing product in short order.
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